The present invention relates in general to semiconductor memories, and in particular to an improved word line driving structure that reduces power consumption and chip area.
Semiconductor memory circuits are made up of one or more memory arrays each including memory cells located at intersections of rows (or word lines) and columns (or bit lines). A memory cell is accessed by asserting a word line and then selecting a bit line. A word line is selected by applying a row address signal to the memory device. The address signal is decoded by a row decoder whose output selects the addressed row. Using a dynamic random access memory (DRAM) circuit as an example, in each array, a single word line may drive 1024 or 2048 memory cell access transistors. FIG. 1 shows a simplified partial schematic of the word line structure for a conventional DRAM. In the typical example shown in FIG. 1, the output of a row decoder 100 drives four word line drivers 102-A, 102-B, 102-C, and 102-D. The output of each word line driver 102 connects to all of the gate terminals of the memory cell (104) access transistors 106 connected to that word line. The gate terminals of these access transistors are typically made of polysilicon, or variations on the polysilicon material (e.g., polycide). Thus, in a tvpical DRAM design, a single polysilicon line that forms the gate terminals of all memory cell access transistors common to a word line, acts as the word line.
Because of the relatively higher sheet resistance of polysilicon material, in larger arrays, metal strapping of the polysilicon word line became necessary to reduce propagation delays through the word line. A strapped polysilicon word line includes a second less resistive conductive layer, typically metal, routed over the poly layer, making contacts with the poly layer at various intervals as shown in FIG. 1. The length of the word line, silicon area consumed by the metal-to-poly contact regions, and acceptable propagation delay are among the factors that dictate the strapping intervals.
Over the years, increasingly higher density memory devices have been made possible by significant reductions in the size of the memory cell. The photolithography aspect of semiconductor processing technology, however, has met with more limited success. It has, therefore, not been possible to shrink the width and spacing of interconnect lines (e.g., metal lines) at the same rate as the size of the memory cell. As a result, at higher densities of, for example, 64 Megabits, the metal-to-metal spacing (or metal pitch) as required by the word line strapping technique has become the limiting factor in determining the size of the memory array. Thus, with the 64 Megabit generation of DRAMs, it became necessary to devise methods to overcome the word line metal pitch limitations.
One approach to relaxing the metal pitch requirement has been to use a hierarchical word line structure with a global (array long) metal word line driving segmented (shorter) polysilicon sub-word lines. In this structure, the word line decoder output (node N1 in FIG. 1) is used as the global word line (GWL) which is routed with its complement as a pair of metal lines across the entire array. Each segment or sub-word line is driven by a dedicated group of sub-word line drivers. Thus, each complementary pair of GWLs typically drives several groups of four sub-word line driver circuits distributed at various locations (segment intervals) across the array. With four sub-word lines thus sharing two metal lines, this structure improves word line density per metal pitch by a factor of two.
However, because this structure requires metal lines carrying complementary signals to be routed in parallel at minimum spacing, a metal-to-metal short would cause dissipation of excessive amounts of standby current. Several other techniques have since been proposed that minimize or eliminate this risk. These techniques typically route a single metal GWL across the array, and include additional circuitry at the local sub-word line driver regions to drive four polysilicon sub-word lines. The GWL signal usually requires a boosted level and the additional circuitry includes extra transistors as well as bus lines to be routed across the array. While these schemes have improved word line density per metal pitch by yet another factor of two (1 metal line shared by 4 poly word lines), the improvement has been realized at the cost of more complexity, appreciably higher power consumption, and larger silicon area.
There is therefore a need for an improved word line driving structure for memory circuits that takes less silicon area and dissipates less power.